1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and in particular to a semiconductor device having a super-junction structure and a method of fabricating the same.
2. Related Art
Vertical power MOSFET has been proposed as a high voltage MOS field effect transistor (MOSEET). Important characteristics of this sort of high voltage MOSFET include ON resistance and breakdown voltage resistance. The ON resistance and the breakdown voltage resistance depend on resistivity of an electric field relaxing layer, wherein the ON resistance can be lowered by raising an impurity concentration in the electric field relaxing layer to thereby lower the resistivity, but this concomitantly lowers the breakdown voltage resistance in a trade-off manner.
In recent years, there has been proposed a super-junction structure as a technique of reducing the ON resistance of the high voltage MOSFET while maintaining the breakdown voltage resistance unchanged.
FIG. 7 is a sectional view showing a configuration of a conventional semiconductor device having such super-junction structure. A semiconductor device 10 has a semiconductor substrate 11, an N-type drift region 14, a base region 15, source regions 22 formed in the base region 15, a gate insulating film 20, a gate electrode 18 formed on the gate insulating film 20, an insulating film 24 formed on the gate electrode 18, a source electrode 26, a P-type column region 16, and a drain electrode 12. The N-type drift region 14 is formed on the semiconductor substrate 11 and functions as an electric field relaxing layer. The base region 15 is formed in the surficial portion of the N-type drift region 14. The source electrode 26 is formed on the insulating film 24 so as to be connected with the source regions 22. The P-type column region 16 is formed between two adjacent portions of the gate electrode 18 in the N-type drift region 14. The drain electrode 12 is formed on the back surface of the semiconductor substrate 11.
The semiconductor substrate 11, the N-type drift region 14, and the source region 22 are designed to have the same conductivity type (N-type in this case). The base region 15 and the P-type column regions 16 are configured as having a conductivity type opposite to that of the N-type drift region 14 (P-type in this case). The N-type drift region 14 and the P-type column region 16 are configured as having almost equal dose of the respective impurities.
Next paragraphs will describe operations of thus-configured semiconductor device. When reverse bias voltage is applied between the drain and the source under no bias voltage applied between the gate and the source, a depletion layer expands from two pn junctions between the base region 15 and the N-type drift region 14, and between the P-type column region 16 and the N-type drift region 14, so that current does not flow between the drain and the source, and the device turns off. More specifically, the interface between the P-type column region 16 and the N-type drift region 14 extends in the depth-wise direction, from which the depletion layer extends, so that depletion of the region over a width of d, shown in FIG. 7, means depletion of the entire portion of the P-type column region 16 and the N-type drift region 14.
The breakdown voltage resistance of the semiconductor device can therefore be made independent of concentration of the impurity of the N-type drift region 14 which functions as an electric field relaxing layer, if the P-type column region 16 and the N-type drift region 14 are specified so as to thoroughly shrink the width d. Adoption of the super-junction structure as described in the above makes it possible to maintain the breakdown voltage resistance, while keeping the ON resistance low by raising the concentration of impurity of the N-type drift region 14. Japanese Laid-Open Patent Publication No. 2001-135819 discloses a super-junction semiconductor device having this sort of super-junction structure.
Japanese Laid-Open Patent Publication No. 2003-273355 (FIGS. 1 and 2) discloses a configuration of a semiconductor device having an N-type drift layer and a P-type drift layer formed so as to extend not only to the cell region but also to the vicinity of the circumference of the junction-end region. On the P-type drift layer in the vicinity of the interface with the cell region out of the junction-end region, there is formed a P-type base layer. On the surface of the junction-end region, but except on a part of the P-type base layer, an insulating film is formed, and further on the insulating film, a field electrode is formed so as to surround the cell region, to contact with the surface of the P-type base layer, and to be electrically connected to the source electrode. More specifically, the field electrode is formed on the P-type drift layer in the vicinity of the interface with the cell region out of the junction-end region.
It is to be noted herein that the narrower the pitch of the column regions becomes, the larger the super-junction effect grows. In particular, for those devices having a low voltage resistance between the source and the drain (approximately 100 V or below, for example), it is preferable to form a micro-super-junction structure. The P-type column regions 16 even formed as having a narrow pitch therebetween, however, result in lateral expansion due to diffusion of the impurity contained in the P-type column regions 16 into the N-type drift region 14, if it is exposed to a large thermal history, and this makes it difficult to narrow the pitch.
For the semiconductor device having the micro-super-junction structure, it is therefore necessary to investigate into the process steps of fabrication successfully preventing the semiconductor device from being exposed to thermal stress after formation of the P-type column regions 16.